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A number of process integration issues arise in the formation of L D D structures. The spacer width is an important parameter and must be fairly tightly controlled. 2 |xm wide spacer using a process such as that described above with acceptable uniformity. Another problem arises from the so-called 1 2 1 3 + + - 2 48 Alan G. Lewis and John Y. Chen Thermal oxide (a) / p-substrate (b) (c) O x i d e spacer (e) Fig. 3. Process sequence for forming N M O S L D D structures: (a) Polysilion-gate definition, (b) H-implant, (c) oxide deposition, (d) spacer etch, and (e) n implant and anneal.

Firstly, oxygen can be diffused under the gate a short distance, thickening the gate dielectric there and forming a graded-gate-oxide ( G G O ) region. Secondly, the heavily doped polysilicon gate oxidizes much faster than the lightly doped single-crystal 49 2. i Position a l o n g surface Fig. 4. et al Channel electric fields with conventional and lightly doped drains. ) material, causing significant shrinkage of the gate, and potentially leaving a gap between the gate edge and the ^-region. These effects are illustrated in Fig.

Cheng and E. A. Sullivan, Effect of Coulombic scattering on silicon surface mobility. /. Appl. Phys. 45, 187 (1974). Y. C. Cheng and E. A. Sullivan, Surf. Sci. 34, 717 (1973). B. Hofflinger, H. Sibber, and G. Zimmer, Model and performance of hot-electron MOS transistors for VLSI. IEEE Trans. Electron Devices ED-26, 513-520 (1979). A. G. Sabnis and J. T. Clemens, Characterization of electron velocity in the inverted (100) Si surface. Tech. —Int. , pp. 18-21 (1979). 36 19. Ping K. Ko S. C. Sun and J.