CMOS PLL Synthesizers: Analysis and Design by Keliu Shu, Edgar Sanchez-Sinencio

By Keliu Shu, Edgar Sanchez-Sinencio

This booklet provides either basics and the cutting-edge of PLL synthesizer layout and research suggestions. a whole review of either system-level and circuit-level layout and research are lined. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is applied in 0.35m m CMOS. It includes a high-speed and strong phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on velocity and integration bottlenecks of PLL synthesizer elegantly. This e-book is conceived as a PLL synthesizer guide for either academia researchers and layout engineers.

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Tri-state phase-frequency detector (PFD) The phase detector (PD) detects the phase difference between the reference signal and the feedback signal from the VCO and frequency divider. Note that, although the PD of a PLL can be an analog multiplier, an exclusive-or (XOR) gate or a J-K flip-flop, etc, for a frequency synthesizer we always use the charge-pump PLL with a tri-state phase-frequency detector (PFD) that also detects frequency errors [3]. Note that, this tri-state PFD is also referred to as “type-4” PD in the literature.

Chapter 3 40 where margin is: and The open-loop phase- For maximum phase margin, we have Therefore, the optimal phase margin is Thus, the maximum phase margin is exclusively determined by the capacitor ratio b . 19) is simplified as: Figure 3-9. Phase margin with variation for different values 3. PLL FREQUENCY SYNTHESIZER 41 In a real PLL, the inaccuracy of resistance and capacitance of an on-chip loop filter and variance of VCO conversion gain affects the phase margin. The variation of resistance and capacitance is typically 10%~20%, while the variation of can be more than a factor of 2.

The resolution of DDS can be made arbitrarily small with very little additional circuitry or added circuit complexity. Due to sampling theory a DDS can only generate frequencies up to a maximum of half of the clock rate of the digital circuitry. The primary disadvantage of most direct digital synthesizers is the typically high spurious content caused by quantization and linearity limitation of the DAC. g. an 8-bit DAC would have quantization spurious 48dB lower than the carrier). However, as Chapter 2 16 the DAC is clocked at frequencies approaching its upper limit, spurs caused by non-linearities in the DAC become dominant [22].

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